The present invention relates to an apparatus and method for performing interrupt management in a computer processing real-time operation system (real-time OS), multitask operation system (multitask OS), and signal processing processor (DSP), and relates in particular to a suitable interrupt management apparatus and interrupt management method used in an image terminal apparatus, etc., such as a portable videophone apparatus or the like, in a mobile communication system using the W-CDMA (Wide band-Code Division Multiple Access) method.
Conventionally, in a microprocessor system, when an asynchronous interrupt request due to a source such as an interrupt request from an external device or external apparatus, or a software interrupt request from an executing application program, (generically termed xe2x80x9cinterrupt requestxe2x80x9d below) is generated while the microprocessor (termed xe2x80x9cCPUxe2x80x9d below) is executing program processing, the executing program processing is suspended and interrupt request processing is performed.
On the other hand, a DSP has an internal main processor (termed xe2x80x9cMPxe2x80x9d below) as an entity corresponding to the above-described CPU, and if an interrupt request is generated while this MP is executing program processing, the executing program processing is suspended and interrupt request processing is performed. Below, the minimum unit of a program is called a task.
As the content of the processing performed in response to an interrupt request differs for each interrupt source, the user must create in advance an interrupt service routine (termed xe2x80x9cinterrupt processing taskxe2x80x9d below) for each interrupt source. An interrupt request is reported to the CPU or MP by control means (called xe2x80x9cinterrupt controllerxe2x80x9d below) that reports the generation of an interrupt. The CPU or MP identifies the interrupt source, calls the corresponding interrupt processing task, and performs processing of the interrupt request.
When task processing being executed by the CPU or MP is suspended due to generation of an interrupt request, the task address at which processing is to be restarted and the contents of CPU or MP internal registers being used up to that time (termed xe2x80x9ccomputational resources currently involved in processingxe2x80x9d below) are saved before the interrupt processing task is executed. Then, when the interrupt processing task ends, these internal registers are restored to their original state, and the task processing that was being executed is restarted.
If processing for saving and restoring computational resources currently involved in processing is written within an above-described interrupt processing task, interrupt processing task creation becomes complicated, and therefore in a microprocessor system that has a CPU, such processing is generally performed by calling a real-time OS or multitask OS (generically termed xe2x80x9cOSxe2x80x9d below) interrupt management facility (referred to below as a xe2x80x9csystem callxe2x80x9d).
In a DSP that has an MP, the above-described interrupt management facility is usually constructed as a monitor program of software of a single individual task separate from the interrupt processing task (in the case of a DSP, usually called microcode or firmware).
Below, the above-described interrupt management facility and the above-described monitor program are given the generic name of xe2x80x9cinterrupt handler.xe2x80x9d
Interrupt processing is classified into single interruption in which acceptance of other interrupts is disabled while interrupt processing is being performed, and multiple interruption in which acceptance of other interrupts is possible even while interrupt processing is being performed.
With single interruption, when an interrupt is generated computational resources currently involved in processing are saved by the interrupt handler to that task""s stack area and task control means, and at the same time, the interrupt mask is masked, disabling other interrupts, and interrupt processing is performed. Then, when interrupt processing is completed and execution of the suspended task is to be resumed, the task stack information, task control means, and interrupt mask are restored.
On the other hand, when multiple interruption is possible, when the interrupt mask is masked to disable other interrupts by the interrupt handler, interrupt masking is not set, and interrupt processing is performed, for higher interrupt levels. That is to say, with an interrupt handler that has multiple interruption capability, if a plurality of interrupts are generated it is necessary to decide which interrupts are to be disabled.
However, in deciding acceptance/disabling of other interrupts within an interrupt task, the interrupt handler and interrupt processing task are closely associated, and there is a problem in that it is not possible for changes to the content of interrupt processing by the interrupt handler and changes to the content of interrupt processing by the interrupt processing task to be carried out independently of each other.
Meanwhile, in deciding acceptance/disabling of other interrupts using an OS, the interrupt handler in the OS decides acceptance/disabling of interrupts en bloc for all interrupt sources, and therefore there is a problem in that the user must create an interrupt processing task while being aware of the interrupt management state of the interrupt handler within the OS. There is a further problem in that it is not possible to construct interrupt processing that does not depend on the interrupt management state of the interrupt handler within the OS.
Unexamined Japanese Patent Publication No. 5-224951 discloses a management method comprising duplicate interruption specifying means for specifying a software interrupt when started by a CPU that receives an interrupt request and shifting processing to the OS before a shift of processing to the interrupt handler, interrupt handler starting means for performing interrupt source analysis and saving of registers within the OS and starting the interrupt handler when processing has been shifted via the duplicate interruption specifying means, and interrupt handler end processing means for performing restoration of registers within the OS and restarting the suspended processing when the end of interrupt processing is reported by the interrupt handler.
According to the management method described in this Unexamined Japanese Patent Publication No. 5-224951, processing for saving and restoring registers within the OS and processing by an interrupt handler can be separated by the duplicate interruption specifying means, and an improvement in interrupt handler creation efficiency can be achieved. However, there is a problem in that nothing is disclosed concerning means for separating the interrupt handler and interrupt processing task, and it is still not possible for changes to the content of processing by the interrupt handler and changes to the content of interrupt processing by the interrupt processing task to be carried out independently.
Also, Unexamined Japanese Patent Publication No. 8-297581 discloses a technique whereby an interrupt controller is provided that has a plurality of interrupt input means that can be individually masked, and that reports interrupts to the CPU according to input to unmasked interrupt input means; specific interrupt manipulating processing means for manipulating an interrupt mask table in the interrupt controller is provided within the OS; and in addition only information relating to interrupts that it is wished to be managed by the OS is stored in managed interrupt storing means, and in an interval in which exclusive control is performed during OS system call processing, only interrupts for which information is stored in the managed interrupt storing means are disabled, and the interrupt enabled state is continued for interrupts for which a system call is not issued.
According to the technique described in this Unexamined Japanese Patent Publication No. 8-297581, an interrupt task that does not affect resource management by the OS is no longer influenced by the OS, and the processing of that interrupt processing task can be constructed in isolation from the OS. However, there is a problem in that an interrupt processing task related to resource management by the OS is closely associated with OS processing, and, as before, it is necessary to create an interrupt processing task while being aware of the interrupt enabling/disabling processing content in the interrupt handler within the OS.
It is an objective of the present invention to provide an interrupt management apparatus and interrupt management method that enable the content of interrupt processing by an interrupt handler or interrupt processing task to be changed easily when it is necessary to change interrupt handler processing, such as when it is to be made possible for other interrupts to be accepted within an interrupt task, or when other interrupts are to be disabled. It is a further objective of the present invention to provide an interrupt management apparatus and interrupt management method that enable the user to create an interrupt processing task without being aware of the interrupt enabling/disabling processing content in an interrupt handler within the OS when interrupts are managed using the OS, even if the interrupt handler within the OS performs interrupt enabling/disabling processing en bloc for all interrupt sources, and to make it possible to construct interrupt processing that does not depend on the interrupt management state of the interrupt handler within the OS.
These objectives are achieved by providing, independently of an interrupt handler that stipulates processing for each interrupt source, interrupt managing means forholding interrupt acceptance possibility states prepared for each interrupt source, and interrupt mask canceling means for canceling a mask set for an interrupt source for which an interrupt is accepted, wherein the interrupt handler controls interrupt enabling/disabling for each interrupt source by updating the interrupt mask using the above-described interrupt managing means and the above-described interrupt mask canceling means.